module get_instruct
(
	input wire sys_clk,
	input wire sys_rst_n,
	input wire get_inst_en,
	input wire [15:0] ip,
	
	output reg decode_en,
	output reg [15:0] instruct_code
);

reg [15:0] ip_buf;
wire [15:0] instruct_code_wire;

reg rd_en;
reg rd_en_d1;
reg rd_en_d2;

always @(posedge sys_clk or negedge sys_rst_n)
	if (sys_rst_n == 1'b0)
		ip_buf <= 16'h0;
	else if (get_inst_en == 1'b1)
		ip_buf <= ip;
	else
		ip_buf <= ip_buf;

always @(posedge sys_clk or negedge sys_rst_n)
	if (sys_rst_n == 1'b0)
		rd_en <= 1'b0;
	else if (get_inst_en == 1'b1)
		rd_en <= 1'b1;
	else
		rd_en <= 1'b0;

always @(posedge sys_clk or negedge sys_rst_n)
	if (sys_rst_n == 1'b0)
	begin
		rd_en_d1 <= 1'b0;
		rd_en_d2 <= 1'b0;
	end
	else
	begin
		rd_en_d1 <= rd_en;
		rd_en_d2 <= rd_en_d1;
	end

always @(posedge sys_clk or negedge sys_rst_n)
	if (sys_rst_n == 1'b0)
	begin
		decode_en <= 1'b0;
		instruct_code <= 16'h0;
	end
	else if (rd_en_d1 == 1'b1)
	begin
		decode_en <= 1'b1;
		instruct_code <= instruct_code_wire;
	end
	else
	begin
		decode_en <= 1'b0;
		instruct_code <= instruct_code;
	end

ram_disk_256x16	ram_disk_inst (
	.aclr ( ~sys_rst_n ),
	.address ( ip_buf ),
	.clock ( sys_clk ),
	.data ( 16'hz ),
	.rden ( rd_en ),
	.wren ( 1'b0 ),
	.q ( instruct_code_wire )
	);

endmodule